Static random access memories (SRAM) are commonly used in integrated circuits. Embedded SRAM is particularly popular in high speed communication, image processing and system on chip (SOC) applications. SRAM cells have the advantageous feature of holding data without requiring a refresh. Typically, a SRAM cell includes two pass-gate transistors, through which a bit can be read from or written into the SRAM cell. This type of SRAM cell is referred to as a single-port SRAM cell. Another type of SRAM cell is referred to as dual port SRAM cell, which includes four pass-gate transistors. FIGS. 1A, 1B and 1C are circuit diagrams of a six transistor single-port SRAM cell circuit, an eight transistor two-port SRAM cell circuit and an eight transistor dual-port SRAM cell circuit, respectively. As can be seen from the figures, the basic cell includes two cross-coupled inverters including two pull-up (PU) and two pull-down (PD) transistors, which form a data storage latch. One or more pass gate (PG) transistors are coupled between the differential bit lines (BL and BLB) for reading a bit from and/or writing a bit to the SRAM cell latch. The gates of the pass-gate transistors are controlled by a word line.
In deep sub-micron technology, the 6T single-port SRAM faces a speed/shrinkage barrier with respect to cell stability and Vcc-min performance. For cell speed improvement, the key factors are cell current, leakage current, cell N/P ratio, bit line loading and bit line couple effect. These factors determine the speed performance of the SRAM array. Cell stability and Vcc-min performance degrade as the power-supply voltage and cell size continue to shrink. As such, a low bit line coupling/loading effect cell structure will become a key element of embedded memory and SOC products. Having a short bit line reduces this coupling effect and is thus important to cell speed performance. A thin style cell layout (word-line length to bit-line length (i.e., X cell pitch:Y cell pitch) larger than 2 within a unit cell) is used to enhance cell speed.
Also, with the falling power-supply voltage and sizes of SRAM cells, decreasing amounts of charge are stored in the cells and poorer results for soft-error rate (SER) can be expected. In nanometer generations, the SER is a huge concern, likely more so than all the other reliability concerns combined. The SRAM cell design and device features impact the SER performance.
While optimizing SRAM cell device performance, the designer must not only be concerned with device performance, but also with Static Noise Margin (SNM) and transistor mismatch induced cell stability issues. The use of smaller cell transistors in small area cells places increased emphasis on these issues. Cell setting and optimization within a limited cell area is a major concern for realizing future cell shrinkage. In the past, designers used a narrow transistor pitch in the SRAM (when compared to transistor pitch of the surrounding logic transistors) to improve the shrink ratio. However, any gate length shrinkage to realize this narrower transistor pitch had to be accounted for in the device's control capability and data stability.
An improved SRAM design is desired.